1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to an array substrate for a liquid crystal display and a fabrication method thereof.
2. Description of the Related Art
Recently, as modern society quickly changes in an information-oriented society, flat panel displays having many advantages such as slimness, light weight, and low power consumption are widely used. Particularly, among the flat panel displays, liquid crystal displays (LCD) having superior color reproduction have been developed.
As known in the art, a liquid crystal display is formed by the steps of: arranging two substrates each having electrode formed on one surface thereof to face with each other; and injecting liquid crystal material between two substrates. In the liquid crystal display, images are displayed by rearranging liquid crystal molecules by an electric field generated by a voltage applied to two electrodes to vary light transmittance.
In the above liquid crystal display, a lower substrate is an array substrate including a thin film transistor for applying a signal to a pixel electrode and is formed by repeating a metallic film and insulating film forming step and a lithography step. Further, an upper substrate is a substrate including a color filter layer of three colors of red, green and blue sequentially arranged and is manufactured using a pigment dispersion method, a dyeing method, an electro deposition method, etc.
Generally, an active layer of the thin film transistor is formed of amorphous silicon (a-Si:H). This is because the amorphous silicon is easily fabricated in a large-sized structure, thereby resulting in a higher productivity, and the amorphous silicon can be deposited on the substrate at a lower temperature below 350° C., thereby permitting use of a lower price insulating substrate.
However, because a hydrogenated amorphous silicon is in disordered atomic arrangement due to a weak Si—Si bond and a dangling bond, when light is radiated on or an electric field is applied to the hydrogenated amorphous silicon, it is changed to be in a meta-stable state, so that when the amorphous silicon is used in the thin film transistor, questionable stability results.
In particular, the amorphous silicon has a disadvantage in which deterioration is caused by light radiation. Further, because a driving unit for a display pixel has an electric characteristic (low field effect mobility:0.1˜1.0 cm2/V·s) that causes the reliability to deteriorate, the amorphous silicon is difficult to use in a driving circuit.
Further, if a liquid crystal panel for the liquid crystal display increases in resolution, the pad pitch external to the substrate is narrowed for connecting a gate line and a data line of a thin film transistor substrate with a tape carrier package (TCP), so that TCP bonding itself becomes difficult.
However, because polycrystalline silicon has a field effect mobility larger than the amorphous silicon, the driving circuit can be formed directly on the substrate, which decreases the manufacturing cost for a driving integrated circuit and simplifies the mounting structure of the driving IC.
Further, the above polycrystalline silicon has the advantages that the field effect mobility is one hundred to two hundreds times larger than that of the amorphous silicon, the response speed is fast, and the stability is excellent with respect to temperature and light. Furthermore, the polycrystalline silicon has the advantage that the driving circuit can be formed on the same substrate.
Various fabrication methods of polycrystalline silicon having the above advantages are known in the art. Typically, to form polycrystalline silicon, amorphous silicon is deposited through a plasma enhanced chemical vapor deposition or a low pressure chemical vapor deposition, and the deposited amorphous silicon is again crystallized.
As one method of forming polycrystalline silicon uses a laser annealing method in which the substrate is heated to a temperature of about 250° C. while an excimer laser radiates a thin amorphous silicon film to form the polycrystalline silicon. Another crystallizing method is a metal induced crystallization (MIC) method in which a metal deposited on the amorphous silicon is used as a seed to form the polycrystalline silicon. Another crystallizing method is a solid phase crystallization (SPC) method in which the amorphous silicon is heated for a long time at a high temperature to form the polycrystalline silicon, etc.
On the other hand, in order to provide a reliable thin film transistor, it is important to form a larger crystalline grain. One method for solving this is a single crystalline forming method (Robert S. Sposilli, M. A. Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956˜957, 1997) using a sequential lateral solidification (SLS) crystallization technique that uses the fact that the silicon crystalline grain grows up from a boundary surface between a liquid-phase silicon and a solid-phase silicon in a vertical direction.
In the SLS crystallization technique, the magnitude of the laser energy, and the range and the translation distance of the laser beam are properly controlled such that the silicon crystalline grain can be laterally grown-up by a predetermined length to allow the amorphous silicon to be crystallized as a single crystalline silicon.
Hereinafter, with reference to the attached drawings, a conventional array substrate and fabrication method thereof will be described including a polycrystalline silicon thin film transistor.
FIGS. 1A and 1B are sectional views respectively illustrating conventional top-gate type thin film transistors of a pixel and a driving circuit, and the pixel and the driving circuit all employ a top-gate type thin film transistor in which a gate electrode is positioned over a semiconductor layer.
First, in a pixel thin film transistor (I) of FIG. 1A, a buffer layer 114 is formed on a whole insulating substrate 100, a semiconductor layer 116 is formed on the buffer layer 114, and then a gate insulating layer 118 and a gate electrode 120 are sequentially formed on a central portion of the semiconductor layer 116.
Further, an interlayer insulating layer 124 having first and second semiconductor layer contact holes 122a and 122b formed therein is formed on the whole resultant substrate having the gate electrode 120. Additionally, source and drain electrodes 126 and 128 are formed to connect with the semiconductor layer 116 through the first and second semiconductor layer contact holes 122a and 122b. 
Furthermore, a passivation layer 132 having a drain contact hole 130 formed therein is formed on the resultant substrate having the source and drain electrodes 126 and 128, and a pixel electrode is formed on the passivation layer to connect with the drain electrode 128 through the drain contact hole 130.
The semiconductor layer 116 includes an active layer 116a formed in a region corresponding to the gate insulating layer 118, and an N+ doped N-type impurity layer 116c formed in a contact region with the source and drain electrodes 126 and 128. In a junction portion between the source and drain electrodes 126, 128 between the active layer 116a and the N-type impurity layer 116c and the gate electrode 120, a lightly doped drain (LDD) layer 116b is located.
The LDD layer 116b is doped with a lower concentration for the purpose of dispersing hot carriers so as to prevent a leakage current from increasing and to minimize a current loss in an ON state.
In FIG. 1B, a complimentary metal-oxide-silicon (CMOS) thin film transistor includes a thin film transistor (II) having an N doped channel and a thin film transistor (III) having a P doped channel, and for description convenience, the same elements are numbered in a sequence of II and III.
As shown in FIG. 1B, an N-type semiconductor layer 140 and a P-type semiconductor layer 142 are formed on the insulating substrate 100 having the buffer layer 114 formed. Herein, the gate insulating layers 144a and 144b and the gate electrodes 146a and 146b are respectively formed on the N-type and P-type semiconductor layers 140 and 142. Additionally, the interlayer insulating layer 124 having the semiconductor layer contact holes 147a, 147b, 147c and 147d formed therein is formed on the whole resultant substrate having the gate electrodes 146a and 146b. 
Source and drain electrodes 150a, 152a, 150b and 152b are respectively formed on the interlayer insulating layer 124 to connect with the N-type and P-type semiconductor layers 140 and 142 through the semiconductor layer contact holes 147a, 147b, 147c and 147d, and the passivation layer 132 is formed on the whole resultant substrate having the source and drain electrodes 150a, 152a, 150b and 152b. 
The N-type semiconductor layer 140 includes, as in the semiconductor layer 116 of FIG. 1A, an active layer 140a formed in a contact region with the gate insulating layer 144a, an N-type impurity layer 140c formed in a region including a contact region with the source and drain electrodes 150a and 152a, and an LDD layer 140b between the active layer 140a and N-type impurity layer 140c. 
Hereinafter, a conventional fabrication method will be described for a general thin film transistor of the pixel and a CMOS thin film transistor of the driving circuit.
FIG. 2 is a process flow chart illustrating a conventional fabrication method of a top-gate type thin film transistor of FIGS. 1A and 1B, and this fabrication method includes a photolithography step (hereinafter, “masking process”) using a photoresist (PR).
First, the insulating substrate is prepared, and the buffer layer is formed on the insulating substrate S100. For the material of the buffer layer, an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx) may be used.
Next, the active layer is formed on the buffer layer S11. In this step, the amorphous silicon (a-Si) layer is deposited to have a thickness of about 550 Å on the resultant substrate having the buffer layer formed, and then a dehydrogenation process is performed. Additionally, through a crystallization process, a crystalline silicon layer is formed such as a polycrystalline silicon layer or a single crystalline silicon layer, and then the crystalline silicon layer is used to form the active layer by a first masking process.
After that, the gate insulating layer and the gate electrode are formed S120. A silicon nitride film with a thickness of about 1000 Å and a molybdenum (Mo) film with a thickness of about 2000 Å are sequentially deposited on the resultant substrate having the active layer formed, and then through a second masking process, the gate insulating layer and the gate electrode are formed.
Next, a step is performed for completing the N-type semiconductor layer. That is, the N− doped LDD layer is formed on the resultant substrate having the gate electrode, the gate insulating layer is formed, and then through a third masking process, the N+ doped N-type impurity layer is formed S130.
Next, the P+ doped P-type impurity layer is formed on the resultant substrate having the N-type impurity layer formed therein, through a fourth masking process S140.
Further, a step is performed for forming the interlayer insulating layer S150. The inorganic insulating film with a thickness of about 7000 Å may be silicon nitride or silicon oxide and is deposited on the resultant substrate having the P-type impurity layer formed, and then through a fifth masking process, the interlayer insulating layer having the semiconductor layer contact hole is formed.
Next, molybdenum (Mo) with a thickness of about 500 Å and aluminum neodymium (AlNd) with a thickness of about 3000 Å are sequentially deposited on the resultant substrate with the interlayer insulating layer, and then through a sixth masking process, a blanket etching is performed to form the source and drain electrode to connect with the impurity layer through the semiconductor layer contact hole S160.
Further, the silicon nitride film with a thickness of about 4000 Å is deposited to form the passivation layer on the resultant substrate with the source and drain electrodes, and then a hydrogenation heat-treatment process is performed. The hydrogenation heat-treatment process may be performed once using nitrogen (N2) gas at a temperature of change about 380° C.
Next, through a seventh masking process, the drain contact hole is formed in the passivation layer S170.
Finally, the pixel electrode is formed on the passivation layer S180. In this step, a layer of Indium Tin Oxide (ITO) about 500 Å thick is deposited on the resultant substrate having the passivation layer formed, and then through an eighth masking process, the pixel electrode is formed to connect with the drain electrode through the drain contact hole.
One problem as the liquid crystal display increases size and increases in resolution, the length of the lines lengthen and a width thereof are narrowed thereby resulting in increasing a probability of a signal delay.
Accordingly, there remains a need to decrease the resistance of the lines using a low resistance material.